Power semiconductors, starting from a critical temperature of the semiconductor junction, which can also be referred to as TJ (“junction temperature”), exhibit a significant reduction (“derating”) of lifetime and performance. Typical power semiconductors include, for example, light-emitting diodes (LEDs), in particular so-called high-power LEDs, integrated circuits (IC) such as, for example, high-power graphics chips, power amplifiers and power transistors such as, for example, power MOSFETs and IGBTs. A derating begins typically at a temperature TJ of approximately 105° C., for example, in the case of high-power LEDs, and typically at a temperature TJ of approximately 175° C. in the case of IGBTs. In the case of LEDs, in particular, there is the risk not only of reduction of the lifetime of the power semiconductor per se, but also of degradation of phosphor-silicone layers used, for example, as a result of which the light spectrum of an LED could change in an undesirable manner.
In conventional system solutions, the temperature of the power semiconductor during operation is often not known accurately enough, and so the power has to be limited to a safety value that is usually 85 to 90% of the maximum usable power. A further increase in power without the risk of a derating requires a thermally optimized carrier and temperature monitoring.
Efficient temperature management is becoming more and more important in the case of LEDs, for example, in the dimensioning of the light power, in particular the maximum achievable light power (in lumens/watt). On account of the limited modeling accuracies of the carrier system, the temperature of LEDs has to be regulated downward to 85 to 90° C., such that the LEDs cannot be operated with maximum power at the—with regard to derating—maximum possible temperature of typically 105° C. This results in performance losses of approximately 5% per 10° C. lower temperature.
In the case of solutions in accordance with the prior art, by way of example, power semiconductors and a temperature sensor are applied alongside one another on a ceramic carrier or silicon carrier, wherein one or a plurality of power semiconductors are placed on a planar surface of a carrier on which a temperature sensor element is also arranged. The power semiconductors here can in each case also comprise individual carriers (“level-1 carriers”), with which they are applied to the common carrier (“level-2 carrier”). Mounting on a heat sink is effected in turn by way of the common carrier. As a result, at a multiplicity of interfaces such as soldering connections, for instance, thermal resistances and junction conductances arise, and they can be described usually relatively inaccurately. The temperature measured by the temperature sensor alongside the one or the plurality of power semiconductors is determined by the thermal resistances and the junction conductances between the individual component parts and by the heat conduction in the individual component parts, such as, for instance, in the common carrier and in the heat sink, and thus to a certain degree constitutes only an indirect measurement. As a result of the additional arrangement of a temperature sensor on a common carrier with one or a plurality of power semiconductors, an increased space requirement and hence a larger structural size are additionally accepted as well.